Method of manufacturing a semiconductor device having an even coating thickness using electro-less plating and related device

ABSTRACT

A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

CROSS REFERENCE TO RELATED APPLICATION

This is a divisional application based on pending application Ser. No.12/073,310, filed Mar. 4, 2008, the entire contents of which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments relate to a method of manufacturing a semiconductor deviceand, more particularly, to a method of manufacturing a semiconductordevice having an even coating thickness using electro-less plating, anda device made thereby.

2. Description of the Related Art

Generally, electroplating and electro-less plating may be used todeposit a material layer, e.g., a conductive layer, on a substrate.Electroplating typically involves exposing a target substrate to ametal-containing solution, in which metal ions are dissolved in acid,and driving a reduction reaction using an applied electric potential soas to convert the metal ions to a metal layer on the substrate. Forexample, the substrate may be immersed in the metal-containing solutionwhile being connected as a cathode of the electrical circuit. Thecathode may be connected to a first pole of a power source, and an anodeconnected to an opposite pole of the power source may be immersed in thesolution to complete an electrical circuit.

Unlike conventional electroplating, electro-less plating does not dependon the application of an external electrical potential to drive theplating process. Electro-less plating may be a desirable alternative toelectroplating, because the relatively simple electro-less platingprocess may require less equipment and lower costs as compared toelectroplating. Further, electro-less plating may be employed to form ametal layer on sidewalls and a top portion of a bump, whereaselectroplating may form a metal layer only on the top portion of thebump.

It is commonly understood that even non-conductive substrates may beplated using electro-less plating, i.e., conductivity of the substrateis not required. However, where finely-patterned features are to beplated using electro-less plating, a difference in electrical potentialbetween similar features formed on the substrate may result in thosefeatures being unevenly plated. Thus, in the fabrication of asemiconductor device having finely-patterned features such as, e.g.,bumps, wiring patterns, etc., variations in plating thickness may occurwhen using an electro-less plating process, and the variations inplating thickness may reduce the reliability of the semiconductordevice.

SUMMARY OF THE INVENTION

Embodiments are therefore directed to a method of manufacturing asemiconductor device having an even coating thickness using electro-lessplating, and a related device, which substantially overcome one or moreof the problems due to the limitations and disadvantages of the relatedart.

Embodiments therefore provide a method of electro-less plating suitablefor plating features that are located in regions of a substrate thatcontain impurities of differing types.

Embodiments also provide a device including features having an outerconductive layer, the features being located in regions of a substratethat contain impurities of differing types.

At least one of the above and other advantages may be realized byproviding a method of manufacturing a semiconductor device, includingforming a diffusion barrier layer on a substrate, and forming at leasttwo features on the substrate such that the diffusion barrier layer isrespectively disposed between each feature and the substrate andcontacts the at least two features. A first impurity region of thesubstrate may contain impurities of a first type, a second impurityregion of the substrate may contain impurities of a second type,different from the first type, a first feature of the at least twofeatures may be in the first impurity region, and a second feature ofthe at least two features may be in the second impurity region, suchthat the second feature is electrically isolated from first feature bythe different impurity regions.

The diffusion barrier layer may provide an electrical path between theat least two features, and the method may further include electro-lessplating an outer conductive layer on the at least two features while theat least two features are connected by the electrical path, and, afterthe electro-less plating, processing the diffusion barrier layer so asto interrupt the electrical path. Processing the diffusion barrier layerso as to interrupt the electrical path may include removing thediffusion barrier layer from a region surrounding at least one of the atleast two features. After interrupting the electrical path, thediffusion barrier layer may extend laterally to an outer edge of theconductive layer and is exposed by the conductive layer.

The conductive layer may be plated on a surface of the features thatincludes one or more of copper or nickel, the conductive layer mayinclude one or more of nickel, gold, palladium, tin, or indium, and thediffusion barrier layer may include one or more of titanium, chromium,or aluminum. The conductive layer may include a palladium layer on thesurface of each feature, a nickel layer on each palladium layer, and atleast one gold layer on each palladium layer.

The method may further include, after forming the diffusion barrierlayer and before the electro-less plating, forming a seed layer on thesubstrate, selectively forming the at least two features on the seedlayer, and selectively removing the seed layer from a region between theat least two features. The at least two features may be formed byelectroplating or electro-less plating. Forming the at least twofeatures may include forming a seed layer on the substrate, forming aphotoresist pattern on the substrate, the photoresist pattern havingopenings corresponding to the at least two features, the openingsexposing the seed layer, depositing a material in the openings in thephotoresist pattern using electroplating, planarizing the depositedmaterial to form the at least two features, removing the photoresistpattern, and removing portions of the seed layer exposed on thesubstrate adjacent to the at least two features. The seed layer may beconductive.

A portion of the diffusion barrier layer that provides the electricalpath may be exposed during the electro-less plating. The method mayfurther include, before the electro-less plating, subjecting the exposedportion of the diffusion barrier layer that provides the electrical pathto an oxygen plasma surface treatment.

At least one of the above and other advantages may also be realized byproviding a semiconductor device, including a substrate, at least twofeatures on the substrate, each including an outer conductive layer, anda diffusion barrier layer respectively disposed between each feature andthe substrate, wherein a first impurity region of the substrate containsimpurities of a first type, a second impurity region of the substratecontains impurities of a second type, different from the first type, afirst feature of the at least two features is in the first impurityregion, a second feature of the at least two features is in the secondimpurity region, such that the second feature is electrically isolatedfrom first feature by the different impurity regions, and eachrespective diffusion barrier layer may extend laterally to an outer edgeof the corresponding conductive layer and may be exposed by thecorresponding conductive layer.

The conductive layer may contact a top surface of the diffusion barrierlayer. Each feature may include a core material having a differentcomposition from the conductive layer. The core material may include oneor more of copper or nickel. The conductive layer may include one ormore of nickel, gold, palladium, tin, or indium. The diffusion barrierlayer may include one or more of titanium, chromium, or aluminum. Thediffusion barrier layer may include one or more of a titanium-nitrogencompound or a titanium-tungsten compound.

The at least two features may be bumps that are configured to provideelectrical signals between the semiconductor device and a secondsubstrate. The at least two features may be wiring lines.

At least one of the above and other advantages may also be realized byproviding a display device, including a display and a display driverintegrated circuit coupled to the display, wherein the display isconfigured to reproduce an image in response to signals provided by thedisplay driver integrated circuit, and the display driver integratedcircuit includes a substrate, at least two features on the substrate,each including an outer conductive layer, and a diffusion barrier layerrespectively disposed between each feature and the substrate, wherein afirst impurity region of the substrate contains impurities of a firsttype, a second impurity region of the substrate contains impurities of asecond type, different from the first type, a first feature of the atleast two features is in the first impurity region, a second feature ofthe at least two features is in the second impurity region, such thatthe second feature is electrically isolated from first feature by thedifferent impurity regions, and each respective diffusion barrier layermay extend laterally to an outer edge of the corresponding conductivelayer and may be exposed by the corresponding conductive layer.

At least one of the above and other advantages may also be realized byproviding a method of manufacturing a semiconductor device, includingforming a diffusion barrier layer on a substrate, forming at least twofeatures on the substrate such that the diffusion barrier layer isrespectively disposed between each feature and the substrate, thediffusion barrier layer electrically connecting the at least twofeatures, electro-less plating an outer conductive layer on the at leasttwo features while the at least two features are electrically connectedby the diffusion barrier layer, and selectively removing the diffusionbarrier layer so as to interrupt the electrical connection.

At least one of the above and other advantages may also be realized byproviding a semiconductor device, including a substrate, a first featureand a second feature on the substrate, a first diffusion barrier betweenthe substrate and the first feature, a first conductive layer on thefirst feature, a second diffusion barrier between the substrate and thesecond feature, and a second conductive layer on the second feature,wherein the first conductive layer contacts a top surface of the firstdiffusion barrier, and the second conductive layer contacts a topsurface of the second diffusion barrier.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent tothose of ordinary skill in the art by describing in detail exemplaryembodiments thereof with reference to the attached drawings, in which:

FIG. 1 illustrates a schematic of an electro-less plating operation;

FIGS. 2A-2I illustrate stages in a method of manufacturing asemiconductor device according to a first embodiment;

FIG. 3A illustrates a plan view of an example semiconductor deviceaccording to a second embodiment;

FIG. 3B illustrates a sectional view of the semiconductor device of FIG.3A, taken along a line A-A of FIG. 3A;

FIGS. 4A-4G illustrate cross-sectional views of stages in a method ofmanufacturing the semiconductor device shown in FIG. 3A, taken along aline B-B of FIG. 3A;

FIG. 5 illustrates an example memory card according to a thirdembodiment;

FIG. 6 illustrates an example electronic system according to a fourthembodiment; and

FIG. 7 illustrates an example display device according to a fifthembodiment.

DETAILED DESCRIPTION OF THE INVENTION

Korean Patent Application No. 10-2007-0038981, filed on Apr. 20, 2007,in the Korean Intellectual Property Office, and entitled: “Method for asemiconductor device manufacturing having an even coating thickness inelectro-less plating,” is incorporated by reference herein in itsentirety.

Embodiments will now be described more fully hereinafter with referenceto the accompanying drawings; however, they should not be construed aslimited to the embodiments set forth herein. Rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart.

In the figures, the dimensions of layers and regions may be exaggeratedfor clarity of illustration. It will also be understood that when alayer or element is referred to as being “on” another layer orsubstrate, it can be directly on the other layer or substrate, orintervening layers may also be present. Further, it will be understoodthat when a layer is referred to as being “under” another layer, it canbe directly under, and one or more intervening layers may also bepresent. In addition, it will also be understood that when a layer isreferred to as being “between” two layers, it can be the only layerbetween the two layers, or one or more intervening layers may also bepresent. Where an element is described as being connected to a secondelement, the element may be directly connected to second element, or maybe indirectly connected to second element via one or more otherelements. Further, where an element is described as being connected to asecond element, it will be understood that the elements may beelectrically connected, e.g., in the case of transistors, capacitors,power supplies, nodes, etc. In the figures, the dimensions of regionsmay be exaggerated and elements may be omitted for clarity ofillustration. Like reference numerals refer to like elements throughout.

FIG. 1 illustrates a schematic of an electro-less plating operation.Referring to FIG. 1, a semiconductor device 100 being manufactured mayinclude a substrate 102, e.g., a semiconductor substrate, havingfeatures 116, e.g., bumps 116A and 116B. The features 116 may beconductors that are provided for passing signals, e.g., control signals,data, power, ground, etc. into and out of the semiconductor device 100.The features 116 may be, e.g., bumps on a device bonding pad. In animplementation the features 116 may be, e.g., a signal terminal bump116A and a ground bump 116B.

The semiconductor device 100 may also include device bonding pads 106respectively corresponding to the bumps 116A, 116B. A well region 124,e.g., a doped impurity region, may isolate the bumps 116A from thesubstrate 102. In an implementation, the substrate 102 may be doped withan n-type impurity and the well region 124 may be doped with a p-typeimpurity.

The semiconductor device 100 may also include a diffusion barrier layer108 disposed between the bumps 116A and the bumps 116B. The diffusionbarrier layer 108 may electrically connect one or more bumps 116A to oneor more bumps 116B.

The diffusion barrier layer 108 may serve to normalize a voltagepotential between a bump 116A, which is isolated by the well region 124,and a bump 116B, which is not isolated by the well region 124. Thediffusion barrier layer 108 may reduce or eliminate a voltage potentialbetween the bumps 116A and 116B during electro-less plating. Forexample, where the bump 116A is a signal bump and the bump 116B is aground bump, the voltage potential may be normalized by allowingelectrons to move from the ground bump 116B toward the signal bump 116Athrough the diffusion barrier layer 108.

In view of the electron flow through the diffusion barrier layer 108,each of the bumps 116A and 116B may have an equal or substantially equalsupply of electrons, which may enable an electro-less plating reactionto occur equally at the surface of each of the bumps 116A and 116B, suchthat equal amounts of material, e.g., metal, are deposited on each ofthe bumps 116A and 116B. Accordingly, the electro-less plating processmay yield a plated layer having a substantially uniform thickness withrespect to the bumps 116A and 116B, which may improve the reliability ofthe semiconductor device 100 as compared to an electro-less platingprocess performed when a voltage potential between the bumps 116A and116B is not normalized.

More particularly, in the absence of an electrical connection connectingthe bump 116A to the bump 116B, the bump 116A may not be at a sameelectrical potential as the bump 116B. In particular, the well region124 may isolate the bump 116A from the substrate 102, such that a flowof electrons between the substrate and the bump 116A is different from aflow of electrons between the substrate 102 and the bump 116B. This mayresult in variations in electro-less plating conditions between the bump116A and the bump 116B. For example, electro-less plating may be lesseffective for the bump 116A than for the bump 116B, which is notisolated from the substrate.

FIGS. 2A-2I illustrate stages in a method of manufacturing asemiconductor device according to a first embodiment, including stagesbefore and after the electro-less plating stage illustrated in FIG. 1.In the description that follows, the fabrication of only one bump of thebumps 116A and 116B will be described. However, it will be appreciatedthat fabrication of the other of the bumps 116A and 116B may proceed insimilar fashion. Accordingly, details of the fabrication of the other ofthe bumps 116A and 116B will not be repeated.

Referring to FIG. 2A, the substrate 102 may have the device bonding pad106 thereon. The bonding pad 106 may be in region of the substrate 102that is isolated by an impurity well such as the well 124 describedabove, or may be in a region of the substrate 102 that is not isolated.As shown in FIG. 2A, a passivation layer 104 may be formed on thesubstrate 102. The passivation layer 104 may partially cover the bondingpad 106.

Referring to FIG. 2B, the diffusion barrier layer 108 may be formed onthe passivation layer 104. The diffusion barrier layer 108 may includeone or more of titanium, chromium, or aluminum. In an implementation,the diffusion barrier layer 108 may include one or more of atitanium-nitrogen compound or a titanium-tungsten compound. Thediffusion barrier layer 108 may have a thickness of about 3000 Å. A seedlayer 110 may be formed on the diffusion barrier layer 108. The seedlayer 110 may include copper and may have a thickness of about 2000 Å.The seed layer 110 may act as a seed metal layer for forming a feature116, e.g., a bump, on the bonding pad 106 in a subsequent operation. Forexample, the seed layer 110 may include Ni or a Ni—Cu alloy, and thefeature 116 to be formed later may also include Ni or a Ni—Cu alloy,respectively. In an implementation (not shown), in a case where atitanium layer is used as the diffusion barrier layer 108, the seedlayer 110 may include a titanium nitride layer and a copper layer on topof the titanium nitride layer.

Referring to FIG. 2C, a photoresist layer 114 may be formed on thesubstrate and patterned to define a region in which the feature 116 isto be formed. The photoresist layer 114 may be applied and patternedusing well-known techniques, the details of which will not be repeatedhere. The patterned photoresist layer 114 may expose an area overlyingthe bonding pad 106.

Referring to FIG. 2D, the feature 116 may be formed in the area definedby the patterned photoresist layer 114. The feature 116 may be formedusing, e.g., electroplating or electro-less plating. The feature 116 maybe nickel, copper, a copper-nickel alloy, etc. The feature 116 may beformed to a height less than that of the photoresist layer 114, or maybe formed to a height greater than that of the photoresist layer 114(not shown). In either case, a planarization process may be performed toplanarize the upper surface of the feature 116, as shown in FIG. 2E.Subsequently, the photoresist layer 114 may be removed, as shown in FIG.2F.

Referring to FIG. 2G, portions of the seed layer 110 that are exposedafter removing the photoresist layer 114 may be removed to expose theunderlying diffusion barrier layer 108, e.g., using an etch process. Theetch process may selectively remove the seed layer 110 with respect tothe diffusion barrier layer 108, such that the diffusion barrier layer108 remains. Selectively removing the seed layer 110 may leave a portion110 a of the seed layer between the diffusion barrier layer 108 and theoverlying feature 116.

In another implementation, as described above, the seed layer 110 mayinclude a titanium layer, and the diffusion barrier layer 108 mayinclude a titanium nitride layer and a copper layer on top of thetitanium nitride layer. In this case, the copper top layer may beremoved to expose the titanium nitride layer, and electro-less plating(described below) may be performed in this configuration. However, ifelectro-less plating deposits material on the titanium nitride layer,the titanium nitride layer may also be removed, and electro-less platingmay be performed with the titanium layer exposed.

The diffusion barrier layer 108 may electrically connect the feature 116to an adjacent feature 116. For example, referring again to FIG. 1, thediffusion barrier layer 108 may electrically connect the bump 116A thatis disposed in the well 124 region of the substrate 102 to the bump 116Bthat is disposed outside the well 124 region.

In an implementation, the exposed region of the diffusion barrier layer108 may be subjected to a surface treatment in order to reduce oreliminate the deposition of material thereon during a subsequentelectro-less plating operation. For example, the exposed region of thediffusion barrier layer 108 may be subjected to an oxygen plasmatreatment, e.g., for a duration of about 60 seconds, which may impartinsulating characteristics to the exposed surface. The oxygen plasmatreatment may increase the sheet resistance of the surface of thediffusion barrier layer 108 by about 0.5% to about 5%. Table 1 belowshows effects of example oxygen plasma de-scum treatments on sheetresistivity of a 3,000 Å thick titanium diffusion barrier layer:

TABLE 1 (Sheet resistivity (Ω/square) of Ti (3,000 Å) as a diffusionbarrier layer) As De-scum De-scum De-scum After deposited 60 s * 1 time60 s * 2 times 60 s * 3 times 4 hours Average 2.064 2.086 2.090 2.0942.096 Max. 2.137 2.161 2.166 2.169 2.172 Min. 2.004 2.024 2.027 2.0312.033

Referring to FIG. 211, a conductive layer 122 may be formed on thesurface of the feature 116. The conductive layer 122 may be formed usingelectro-less plating. The electro-less plating may uniformly form theconductive layer 122 on the feature 116 as well as on one or morefeatures 116 that are electrically interconnected by the diffusionbarrier layer 108. Thus, in the case of, e.g., the bumps 116A and 116Bshown in FIG. 1, the electro-less plating may form the conductive layer122 to a substantially uniform thickness on the bump 116A that isdisposed in a well 124 region of the substrate 102, as well as on thebump 116B that is disposed outside the well 124 region.

The conductive layer 122 may include one or more layers of differingmaterials, or may be a single layer. For example, the conductive layer122 may include a double layer of nickel and gold, a single layer ormultiple layers of gold, multiple layers including nickel, multiplelayers including palladium, a single or multiple layers including tin,tin alloys, indium, etc. In an implementation, the conductive layer 122may include a nickel layer 118 and a gold layer 120 formed on the nickellayer 118. In another implementation, the conductive layer 122 mayinclude a palladium layer 126, a nickel layer 118, a first gold layer120B and a second gold layer 120A, as shown in FIG. 21.

For example, the conductive layer 122 may include the palladium layer126 as the bottommost activation layer, the nickel layer 118, having athickness of, e.g., about 0.4 μm, the first gold layer 120B, having athickness of, e.g., about 0.1 μm, formed by a substitution reactionprocess, and the second gold layer 120A, having a thickness of, e.g.,about 0.3 μm to about 0.4 μm, formed by a reduction reaction process. Indetail, a precleaning operation may be performed, after which thepalladium layer 126 may be formed using, e.g., a catalyst treatment.Subsequently, a nickel layer 118, which may serve as a diffusion barrierlayer, may be formed using, e.g., NiP plating at a temperature of about75° C. to about 90° C. The first and second gold layers 120B and 120Amay be formed using a gold substitution reaction and a gold reductionreaction at a temperature of about 65° C. to about 85° C., respectively.After each operation, a cleaning may be performed using deionized water.Where a tin layer is included in the conductive layer 122, the tin maybe deposited using electro-less plating at about 60° C. after aprecleaning operation that includes cleaning with deionized waterfollowed by soft etching using potassium persulfate, K₂S₂O₈. Thehardness of the feature 116 may be adjusted using a heat treatmentoperation, e.g., heating to a temperature of about 250° C.

After forming the conductive layer 122, exposed portions of thediffusion barrier layer 108 may be removed, leaving a portion 108 a ofthe barrier layer between the passivation layer 104 and the overlyingportion 110 a of the seed layer. Since the exposed portions of diffusionbarrier layer 108 are removed after the conductive layer 122 is formed,the conductive layer 122 may cover the feature 116 and may extend alongsides of the feature 116 to contact a top surface of the diffusionbarrier layer 108, as shown in FIG. 21. In an implementation, theconductive layer 122 may directly contact the diffusion barrier layer108, and may directly contact the remaining portion 108 a of thediffusion barrier layer after the selective removal of the exposedportions. The selective removal of the exposed portions of the diffusionbarrier layer 108 may leave the remaining portion 108 a having a lateralextent that is substantially aligned with the outer periphery of theconductive layer 122. The portion 110 a of the seed layer may becompletely encapsulated by the surrounding conductive layer 122, theoverlying feature 116, and the underlying portion 108 a of the diffusionbarrier layer. Removing the exposed portions of the diffusion barrierlayer 108 may interrupt the electrical path between the features 116.Thus, the diffusion barrier layer 108 may act as a diffusion barrier aswell as provide the electrical path during electro-less plating, and theremaining portion 108 a may remain after the electrical path isinterrupted, so as to serve as a diffusion barrier in resultant device.

A second embodiment will now be described in connection with FIGS. 3A,3B, and 4A-4G. In this embodiment, the feature 116 described above maybe implemented as a wiring pattern, e.g., a redistribution pattern 210,on a semiconductor device 200. FIG. 3A illustrates a plan view of anexample semiconductor device according to the second embodiment. FIG. 3Billustrates a sectional view of the semiconductor device of FIG. 3A,taken along a line A-A of FIG. 3A. Referring to FIG. 3A, theredistribution pattern 210 may redistribute bonding regions such that,for example, peripheral bonding pads 206 are connected to respectiveredistributed bonding pads 212, which may be formed in an interiorregion of the semiconductor device 200.

Referring to FIG. 3B, the bonding pad 206 may be disposed on a substrate202. A passivation layer 204 may be disposed on the substrate 202 andmay partially cover the bonding pad 206. A first dielectric layer 208may be disposed on the substrate 202 so as to cover the passivationlayer 204 and expose a region overlying the bonding pad 206. Theredistribution pattern 210 may be disposed in contact with the bondingpad 206 in the region exposed by the passivation layer 204, and mayextend along a surface of the first dielectric layer 208 towards theregion where the redistributed bonding pad 212 is located. A seconddielectric layer 228 may cover the first dielectric layer 208 and theredistribution pattern 210, and may have an opening exposing a region ofthe redistribution pattern 210 to form the redistributed bonding pad212. A solder ball 214, a bump, etc., may be disposed on theredistributed bonding pad 212 and may provide electrical contact with anadjacent substrate such as a printed circuit board, etc., (not shown).

The redistribution pattern 210 may be formed in similar fashion to thefeatures 116 described above. In particular, an electro-less platingoperation may be performed while multiple redistribution patterns 210are electrically connected by a diffusion barrier 216, which isdescribed in detail below. The electrical connection provided by thediffusion barrier 216 may allow the electrical potential ofredistribution patterns 210 connected thereby to be normalized, whichmay improve the uniformity of a conductive layer formed on theredistribution patterns 210.

FIGS. 4A-4G illustrate cross-sectional views of stages in a method ofmanufacturing the semiconductor device 200 described above in connectionwith FIG. 3A, taken along a line B-B of FIG. 3A. Referring to FIG. 4A,the passivation layer 204 may be formed on the substrate 202. Thepassivation layer 204 may be patterned to expose a portion of thebonding pad 206 (see FIGS. 3A and 3B). The first dielectric layer 208may be formed on the substrate 202 and may cover the passivation layer204. The first dielectric layer 208 may be patterned to expose thebonding pad 206.

The diffusion barrier layer 216 may be formed on the first dielectriclayer 208 and on the exposed portion of the bonding pad 206, and a seedlayer 218 may be formed on the diffusion barrier layer 216. In animplementation, the diffusion barrier layer 216 may include Ti, Cr, Al,TiN, and/or TiW, and the seed layer 218 may include Cu, Ni, and/or Cu—Nialloy. In another implementation, the diffusion barrier 216 and the seedlayer 218 may include a three-layer structure of Ti/TiN/Cu.

Referring to FIG. 4B, a photoresist layer 222 may be formed on the seedlayer 218. The photoresist layer 222 may be patterned to form an openingthat exposes a portion of the seed layer 218 that overlies the bondingpad 206, and which defines a channel in which the redistribution pattern210 is to be formed.

Referring to FIG. 4C, forming the redistribution pattern 210 (see FIGS.3A and 3B) may include electroplating or electro-less plating a materialin the opening in the photoresist layer 222 to form a core pattern 224for the redistribution pattern 210. The core pattern 224 may include,e.g., Cu, Ni, or Cu—Ni alloy, and may be formed by electroplating orelectro-less plating. In an implementation, copper may be plated in theopening to a thickness of, e.g., about 3 μm to about 5 μm. The thicknessof the plated material may be greater or smaller than that of thephotoresist layer 222, and the plated material and photoresist layer 222may be planarized in the same manner as described above in connectionwith FIG. 2E. The remaining photoresist layer 222 may then be removed,as shown in FIG. 4D.

Referring to FIG. 4E, portions of the seed layer 218 that are exposed asa result of the removal of the photoresist layer 222 may be selectivelyremoved from around the core pattern 224, e.g., using an etch process,such that the core pattern 224 and the remaining portion 218 a of theseed layer are substantially coextensive. As described above inconnection with the first embodiment, the removal of the seed layer 218may be selective with respect to the underlying diffusion barrier layer216, such that the diffusion barrier layer 216 remains and provides anelectrical path between multiple core patterns 224 at this stage in theexemplary redistribution pattern forming process. Accordingly, asubsequent operation of electro-less plating an outer layer on the corepatterns 224 may be performed while the core patterns 224 areelectrically connected. Thus, the electro-less plating may be used toproduce redistribution patterns 210 that have an outer layer platedthereon that has a substantially uniform thickness.

In an implementation, the surface of the diffusion barrier layer 216 maybe subjected to an oxygen plasma treatment before performingelectro-less plating, which may increase the sheet resistance of thediffusion barrier layer 216 by, e.g., about 0.5% to about 5%.

Referring to FIG. 4F, an outer conductive layer 226 may be plated on thecore pattern 224 using electro-less plating. The outer conductive layer226 may have a thickness of, e.g., about 1 μm to about 3 μm. Asillustrated in FIG. 4F, the outer conductive layer 226 may cover the topand sides of the core pattern 224, such that the core pattern 224 is notexposed in the redistribution pattern 210. This may be particularlyadvantageous in the case of, e.g., a copper core pattern 224, since theouter conductive layer 226 may prevent oxidation of the core pattern 224and may prevent the copper from diffusing into adjacent material layers.

The conductive layer 226 may include one or more layers of differingmaterials, or may be a single layer. For example, the conductive layer226 may include a double layer of nickel and gold, a single layer ormultiple layers of gold, multiple layers including nickel, multiplelayers including palladium, a single or multiple layers including tin,tin alloys, indium, etc. In an implementation, the conductive layer 226may include a nickel layer and a gold layer formed on the nickel layer.In another implementation, the conductive layer 226 may include apalladium layer, a nickel layer, a first gold layer and a second goldlayer, in a similar configuration to that described above in connectionwith FIG. 2I.

For example, the conductive layer 226 may include the palladium layer asthe bottommost activation layer, the nickel layer having a thickness of,e.g., about 0.4 μm, the first gold layer having a thickness of, e.g.,about 0.1 μm, formed by a substitution reaction process, and the secondgold layer having a thickness of, e.g., about 0.3 μm to about 0.4 μm,formed by a reduction reaction process. In detail, a precleaningoperation may be performed, after which the palladium layer may beformed using, e.g., a catalyst treatment. Subsequently, a nickel layer,which may serve as a diffusion barrier layer, may be formed using, e.g.,NiP plating at a temperature of about 75° C. to about 90° C. The firstand second gold layers may be formed using a gold substitution reactionand a gold reduction reaction at a temperature of about 65° C. to about85° C., respectively. After each operation, a cleaning may be performedusing deionized water. Where a tin layer is included in the conductivelayer 226, the tin may be deposited using electro-less plating at about60° C. after a precleaning operation that includes cleaning withdeionized water followed by soft etching using potassium persulfate,K₂S₂O₈. The hardness of the feature may be adjusted using a heattreatment operation, e.g., heating to a temperature of about 250° C.

After the electro-less plating, exposed portions of the diffusionbarrier layer 216 may be selectively removed, leaving a portion 216 a ofthe diffusion barrier layer between the first dielectric layer 208 andthe overlying portion 218 a of the seed layer. Thus, in similar fashionto the first embodiment described above in connection with FIGS. 2A-2I,the conductive layer 226 may cover the copper core pattern 224 and mayextend along sides of the copper core pattern 224 to contact a topsurface of the diffusion barrier layer 216. The conductive layer 226 maydirectly contact the diffusion barrier layer 216, and may directlycontact the remaining portion 216 a of the diffusion barrier layer afterthe selective removal of the exposed portions. The selective removal ofthe exposed portions of the diffusion barrier layer 216 may leave theremaining portion 216 a having a lateral extent that is substantiallyaligned with the outer periphery of the conductive layer 226. Theportion 218 a of the seed layer may be completely encapsulated by thesurrounding conductive layer 226, the overlying copper core pattern 224,and the underlying portion 216 a of the diffusion barrier layer.Removing the exposed portions of the diffusion barrier layer 216 mayinterrupt the electrical path between copper core patterns 224. Thus,the diffusion barrier 216 may act as a diffusion barrier as well asprovide the electrical path during electro-less plating, and theremaining portion 216 a may remain after the electrical path isinterrupted, so as to serve as a diffusion barrier in the resultantdevice.

Referring to FIG. 4G, a second dielectric layer 228 may be formed on thesubstrate 202. The second dielectric layer 228 may be patterned toexpose a top portion of the outer conductive layer 226 of theredistribution pattern 210, the exposed portion corresponding to alocation of the redistributed bonding pad 212 (see also FIG. 3B). Thesolder ball 214, a bump, etc., may be disposed on the redistributedbonding pad 212 to enable an electrical connection to an adjacentsubstrate or element.

FIG. 5 illustrates an example memory card system 700, e.g., amulti-media card (MMC) or a secure digital (SD) card, according to athird embodiment. Referring to FIG. 5, the card 700 may include acontroller 710 and a memory 720. The memory 720 may be, e.g., a flashmemory, a PRAM, a DRAM, etc. An interface may be provided for exchangingdata and commands (instructions) between the controller 710 and thememory 720). Another interface, e.g., a standard MMC or SD interface,may be provided for exchanging information with another device (notshown). The memory 720, the controller 710, and the interfacetherebetween may be packaged together as a multi-chip package (MCP).

FIG. 6 illustrates an example electronic system 800 according to afourth embodiment. Referring to FIG. 6, the system 800 may include aprocessor 810, a memory 820, at least one I/O (input/output) device 830,and at least one bus 840. The system 800 may be, e.g., a mobile phone,an MP3 device, a navigation system, a solid state disk (SSD), ahousehold appliance, etc. The memory 820, the processor 810, the I/Odevice 830, and the bus 840 may be packaged together as an MCP. In animplementation, one, some, or all of the components (memory 820, theprocessor 810 and the I/O device 840) may be packaged together, e.g.,being vertically stacked together as an MCP.

FIG. 7 illustrates an example display device 900 according to a fifthembodiment. The display device 900 may include a display 901 and adisplay driver integrated circuit 902 coupled to the display, e.g.,coupled using an anisotropic conductive film 903. The display 901 may beconfigured to reproduce an image in response to signals provided by thedisplay driver integrated circuit 902. The display driver integratedcircuit 902 may include a substrate, e.g., a semiconductor substrate,having at least two features 916 thereon. The features 916 on thesubstrate may be features as described above having an outer conductivelayer and a diffusion barrier layer respectively disposed between eachfeature and the substrate. A first impurity region of the substrate maycontain impurities of a first type, and a second impurity region of thesubstrate may contain impurities of a second type, different from thefirst type. A first feature of the at least two features may be in thefirst impurity region, and a second feature of the at least two featuresmay be in the second impurity region, such that the second feature iselectrically isolated from first feature by the different impurityregions. Each respective diffusion barrier layer may extend laterally toan outer edge of the corresponding conductive layer and may be exposedby the corresponding conductive layer.

Exemplary embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. Thus,although specific embodiments have been described above whereby a bumpand a redistribution pattern may be plated using an electro-less platingmethod, the method may be similarly applied to other features. Moreover,the method may be applied to a device in which the features, e.g., bumpsor wiring patterns, are not isolated by different impurity regions. Forexample, embodiments may provide a device, e.g., a display driverintegrated circuit in a display device, and a method of manufacturingthe same, in which a diffusion barrier layer is formed on a substrate,at least two features are formed on the substrate such that thediffusion barrier layer is respectively disposed between each featureand the substrate, the diffusion barrier layer electrically connectingthe at least two features, an outer conductive layer is electro-lessplated on the at least two features while the at least two features areelectrically connected by the diffusion barrier layer, and the diffusionbarrier layer is selectively removed so as to interrupt the electricalconnection. The outer conductive layer may contact a top surface of thediffusion barrier layer, the method may include, before forming the atleast two features, forming a seed layer on the diffusion barrier layerin regions corresponding to the at least two features, and a portion ofthe seed layer corresponding to one of the features may be encapsulatedby the outer conductive layer, the feature, and the diffusion barrierlayer.

Accordingly, it will be understood by those of ordinary skill in the artthat various changes in form and details may be made without departingfrom the spirit and scope of the present invention as set forth in thefollowing claims.

1-13. (canceled)
 14. A semiconductor device, comprising: a substrate; atleast two features on the substrate, each including an outer conductivelayer; and a diffusion barrier layer respectively disposed between eachfeature and the substrate, wherein: a first impurity region of thesubstrate contains impurities of a first type, a second impurity regionof the substrate contains impurities of a second type, different fromthe first type, a first feature of the at least two features is in thefirst impurity region, a second feature of the at least two features isin the second impurity region, such that the second feature iselectrically isolated from first feature by the different impurityregions, and each respective diffusion barrier layer extends laterallyto an outer edge of the corresponding conductive layer and is exposed bythe corresponding conductive layer.
 15. The semiconductor device asclaimed in claim 14, wherein the conductive layer contacts a top surfaceof the diffusion barrier layer.
 16. The semiconductor device as claimedin claim 14, wherein each feature includes a core material having adifferent composition from the conductive layer.
 17. The semiconductordevice as claimed in claim 16, wherein the core material includes one ormore of copper or nickel.
 18. The semiconductor device as claimed inclaim 14, wherein the conductive layer includes one or more of nickel,gold, palladium, tin, or indium.
 19. The semiconductor device as claimedin claim 14, wherein the diffusion barrier layer includes one or more oftitanium, chromium, or aluminum.
 20. The semiconductor device as claimedin claim 19, wherein the diffusion barrier layer includes one or more ofa titanium-nitrogen compound or a titanium-tungsten compound.
 21. Thesemiconductor device as claimed in claim 14, wherein the at least twofeatures are bumps that are configured to provide electrical signalsbetween the semiconductor device and a second substrate.
 22. Thesemiconductor device as claimed in claim 14, wherein the at least twofeatures are wiring lines.
 23. A display device, comprising: a displayand a display driver integrated circuit coupled to the display, wherein:the display is configured to reproduce an image in response to signalsprovided by the display driver integrated circuit, and the displaydriver integrated circuit includes: a substrate; at least two featureson the substrate, each including an outer conductive layer; and adiffusion barrier layer respectively disposed between each feature andthe substrate, wherein: a first impurity region of the substratecontains impurities of a first type, a second impurity region of thesubstrate contains impurities of a second type, different from the firsttype, a first feature of the at least two features is in the firstimpurity region, a second feature of the at least two features is in thesecond impurity region, such that the second feature is electricallyisolated from first feature by the different impurity regions, and eachrespective diffusion barrier layer extends laterally to an outer edge ofthe corresponding conductive layer and is exposed by the correspondingconductive layer.
 24. A method of manufacturing a semiconductor device,comprising: forming a diffusion barrier layer on a substrate; forming atleast two features on the substrate such that the diffusion barrierlayer is respectively disposed between each feature and the substrate,the diffusion barrier layer electrically connecting the at least twofeatures; electro-less plating an outer conductive layer on the at leasttwo features while the at least two features are electrically connectedby the diffusion barrier layer; and selectively removing the diffusionbarrier layer so as to interrupt the electrical connection.
 25. Asemiconductor device, comprising: a substrate; a first feature and asecond feature on the substrate; a first diffusion barrier between thesubstrate and the first feature; a first conductive layer on the firstfeature; a second diffusion barrier between the substrate and the secondfeature; and a second conductive layer on the second feature, wherein:the first conductive layer contacts a top surface of the first diffusionbarrier, and the second conductive layer contacts a top surface of thesecond diffusion barrier.